Lateral double-diffused insulated gate field effect transistors (sometimes known as LDMOS transistors) are the power devices of choice for integration into very large scale integrated circuit (VLSI) logic processes. The on-resistance per unit area (r.sub.ds (on)) is the figure of merit for a high voltage power device. Reduced surface field (RESURF) power transistors were introduced by J. A. Appels and H. M. J. Vaes in "High Voltage Thin Layer Devices (Resurf Devices)", IDEM Tech. Dig. 1979, pp. 238-241. RESURF LDMOS device will have, given a (P) type semiconductor substrate, an N-type drift region that surrounds an (N+) drain. Relatively thick LOCOS oxide is grown on a portion of the drift region. A relatively deep (P) type implant is used to make the body of the insulated gate field-effect transistor (IGFET), which spaces the drift region from a source region. A (P+) back gate connection is formed within the (P) body implant region. A conductive gate is formed over and insulated from the IGFET body to extend from the source region over the body to the lateral margin of the LOCOS thicker oxide.
The drift region has a donor dopant concentration N.sub.D1, which is designed to fully deplete with the JFET action from the (P-) substrate gate at the rated voltage. However, the JFET gate dopant concentration is optimized for use of the substrate for other VLSI devices, and is suboptimal for a high voltage power device. A need therefore exists to develop an LDMOS transistor having a low r.sub.ds (on) that is yet compatible with VLSI logic processes.